This application is related to a co-pending application that bears Motorola docket number CR97-133 and U.S. Ser. No. 09/144,686, entitled “MAGNETIC RANDOM ACCESS MEMORY AND FABRICATING METHOD THEREOF,” filed on Aug. 31, 1998, assigned to the same assignee and incorporated herein by this reference, co-pending application that bears Motorola docket number CR 97-158 and U.S. Ser. No. 08/986,764, entitled “PROCESS OF PATTERNING MAGNETIC FILMS” filed on Dec. 8, 1997, assigned to the same assignee and incorporated herein by this reference and issued U.S. Pat. No. 5,768,181, entitled “MAGNETIC DEVICE HAVING MULTI-LAYER WITH INSULATING AND CONDUCTIVE LAYERS”, issued Jun. 16, 1998, assigned to the same assignee and incorporated herein by.
Typically, a magnetic element, such as a magnetic memory element, has a structure that includes ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions that are called “parallel” and “anti-parallel” states, respectively. In response to parallel and anti-parallel states, the magnetic memory element represents two different resistances. The resistance has minimum and maximum values when the magnetization vectors of the two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of change in resistance allows a device, such as an MRAM device, to provide information stored in the magnetic memory element. The difference between the minimum and maximum resistance values, divided by the minimum resistance is known as the magnetoresistance ratio (MR).
An MRAM device integrates magnetic elements, more particularly magnetic memory elements, and other circuits, for example, a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are fabricated in the process of CMOS (complementary metal-oxide semiconductor) technology in order to lower the power consumption of the device.
During typical magnetic element fabrication, such as MRAM element fabrication, metal films are grown by sputter deposition, evaporation, or epitaxy techniques. One such magnetic element structure includes a substrate, a base electrode multilayer stack, a synthetic antiferromagnetic (SAF) structure, an insulating tunnel barrier layer, and a top electrode stack. The base electrode layer stack is formed on the substrate and includes a first seed layer deposited on the substrate, a template layer formed on the seed layer, a layer of an antiferromagnetic material on the template layer and a pinned ferromagnetic layer formed on and exchange coupled with the underlying antiferromagnetic layer. The ferromagnetic layer is called the pinned layer because its magnetic moment (magnetization direction) is prevented from rotation in the presence of an applied magnetic field. The SAF structure includes a pinned ferromagnetic layer, and a fixed ferromagnetic layer, separated by a layer of ruthenium, or the like. The top electrode stack includes a free ferromagnetic layer and a protective layer formed on the free layer. The magnetic moment of the free ferromagnetic layer is not pinned by exchange coupling, and is thus free to rotate in the presence of applied magnetic fields.
During fabrication of these magnetic elements, ion milling is commonly used for the dry etching of the magnetic materials. However, during the process of dry etching, conducting veils are left remaining on the sides of the magnetic tunnel junction (MTJ). These remaining veils lead to electrical shorting of the device between the bottom and top electrodes, more particularly across the insulating tunnel barrier. Currently, wet etching techniques are used in the semiconductor industry to etch away the veils, but are not amenable for use in conjunction with magnetic materials due to their chemical attack on the magnetic materials leading to device performance degradation.
To avoid the shorting problem caused by veils, the current etching process is done in two steps. First the top magnetic layer of the magnetic element is etched or defined, then the whole stack is etched using a dry etch technique; or vice versa. Veils may be minimized by varying the etching beam angle relative to the wafer surface. Since the edges of the top and bottom magnetic layers do not overlap, the veils do not cause a shorting problem between the top and bottom magnetic layers. However, this is a very complex etching process. Stopping the etch of the top magnetic layer without over-etching through the ultra thin tunnel barrier, and into the bottom magnetic layer is very difficult to do. Over-etching into the bottom magnetic layer will cause unwanted magnetic poles shifting the resistance-magnetic field response of the magnetic element. This technique also limits the free magnetic layer to be placed on top of the tunnel barrier.
Accordingly, it is a purpose of the present invention to provide for a magnetic element having formed as a part thereof, insulating veils, which no longer include conductive or magnetic properties.
It is a still further purpose of the present invention to provide a method of forming a magnetic element with insulating veils.
It is another purpose of the present invention to provide a method of fabricating a magnetic element that includes plasma oxygen ashing of the magnetic stack to transform conducting veils into insulating veils.
It is another purpose of the present invention to provide a method of forming a magnetic element with insulating veils which is amenable to simple and high throughput manufacturing.
It is still a further purpose of the present invention to provide a method of forming a magnetic element with insulating veils that allows for the formation of the free magnetic layer anywhere within the magnetic element stack.